The ADC ADC data acquisition component is a monolithic CMOS device with an 8-bit analog-to-digital con- verter 8-channel multiplexer and. ADC ADC – 8-bit Microprocessor Compatible A/D Converters With 8- Channel Multiplexer, Details, datasheet, quote on part number: ADC The ADC/ADC Data Acquisition Devices (DAD) implement on a single chip most the elements of the stan- dard data acquisition system. They contain.

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It is recomended that the source resistance not exceed 5kohms for operation at 1. The ALE should be pulsed for at least ns in order for the addresses to get loaded properly. It is a pulse of at least ns in width. The following control signals are used to control the conversion. The OE signal should conform to the same range as all the other control signals.

National Semiconductor

C is the most significant bit and A is the least. Unfortunately you cannot just hook up analog inputs to an ADC and expect to get digital outputs from the chip without adding control signals. All control signals should have a high voltage from Vcc – 1. As with all control signals it is required to have an input value of Vcc – 1. The clock should conform to the same range as all other control signals.


Up to 72 if the start signal is received in the middle of an 8 clock cycle period. If Vcc and ground are used as reference voltages, they should be isolated by decoupling with a 1 microF capacitor.

ADC Technical Data

Clock The clock signal is required to cycle through the adc8009 stages to do the conversion. It is the Second bit of the select lines.

Top rail of Reference voltage. Control dtaasheet from FPGA. It is the MSB of the select lines. The maximum clock frequency is affected by the source impedance of the analog inputs.

At clock speeds greater than that the user must make certain that enough time has passed since the ALE signal was pulsed so that the correct address is loaded into the multiplexer before a conversion begins. A, B, and C. This is a bit of the digital converted output. The maximum frequence of the clock is 1. The source must remain stable while it is being sampled and should contain little noise. The ADC stores the data in a tri-state output latch until the next conversion is started, but the data is only output datashwet enabled.

Table 2 provides a summary of all of the input and output to the chip. The other files are enabled register, a register, and a multiplexer. There are 8, 8 clock cycle periods required in order to complete an entire conversion. Begin by downloading the files into your desired destination directory and then compile them in this order. Start The purpose of the start signal is two fold. Note that it can take up to 2.


Like the ALE pulse the minimum pulse width is ns. Be sure to consult the manufactures data-sheets for other chips. The minimum pulse width is ns. In this implementation the OE signal is pulsed high one clock cycle after the EOC signal goes high and remains high until the data is safely stored into the desired register in the FPGA.


This means that an entire conversion datqsheet at least 64 clock cycles. See table 1 for details. The source resistance must be below 10kohms for operation below kHz and below 5kohms for operation around 1. It is a control signal from the FPGA, which tells the converter when to start a conversion. There are a couple of limitations that follow: Bottom rail of Reference voltage. All of the signals are explained below.

Address Lines Because the chip has an 8 channel multiplexer there are three address select lines: